// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright (c) 2020 Rockchip Electronics Co., Ltd.
 *
 */
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 *********************************************************************
 * 文件名：tspi-rk3566-dsi-v10.dtsi
 * 描述：mipi 屏幕
 * 更新:
 * 时间          作者           联系           说明
 * 2023-07-21   吴才成    1378913492@qq.com   v1.0.0
 * 2024-01-08   ALU       N/A                 ICN6211 Configuration
  *********************************************************************/
/ {
	backlight: backlight {
		compatible = "pwm-backlight";
		pwms = <&pwm5 0 25000 0>;
		brightness-levels = <
			  0  20  20  21  21  22  22  23
			 23  24  24  25  25  26  26  27
			 27  28  28  29  29  30  30  31
			 31  32  32  33  33  34  34  35
			 35  36  36  37  37  38  38  39
			 40  41  42  43  44  45  46  47
			 48  49  50  51  52  53  54  55
			 56  57  58  59  60  61  62  63
			 64  65  66  67  68  69  70  71
			 72  73  74  75  76  77  78  79
			 80  81  82  83  84  85  86  87
			 88  89  90  91  92  93  94  95
			 96  97  98  99 100 101 102 103
			104 105 106 107 108 109 110 111
			112 113 114 115 116 117 118 119
			120 121 122 123 124 125 126 127
			128 129 130 131 132 133 134 135
			136 137 138 139 140 141 142 143
			144 145 146 147 148 149 150 151
			152 153 154 155 156 157 158 159
			160 161 162 163 164 165 166 167
			168 169 170 171 172 173 174 175
			176 177 178 179 180 181 182 183
			184 185 186 187 188 189 190 191
			192 193 194 195 196 197 198 199
			200 201 202 203 204 205 206 207
			208 209 210 211 212 213 214 215
			216 217 218 219 220 221 222 223
			224 225 226 227 228 229 230 231
			232 233 234 235 236 237 238 239
			240 241 242 243 244 245 246 247
			248 249 250 251 252 253 254 255
		>;
		default-brightness-level = <255>;
	};
};

&pwm5 {
	status = "okay";
};


&pinctrl {
	dsi1 {
		dsi1_rst_gpio: dsi1-rst-gpio {
			rockchip,pins = <3 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
		};
	};
};

/*
 * video_phy1 needs to be enabled
 * when dsi1 is enabled
 */
&dsi1 {
	status = "okay";
};

&dsi1_in_vp0 {
	status = "disabled";
};

&dsi1_in_vp1 {
	status = "okay";
};

&video_phy1 {
	status = "okay";
};

&route_dsi1 {
	status = "okay";//wucaicheng mipi okay
	connect = <&vp1_out_dsi1>;
};

// ICN6211
&dsi1 {
	status = "okay";
  rockchip,lane-rate = <864>;
	dsi1_panel: panel@0 {
		status = "okay";
		compatible = "simple-panel-dsi";
		reset-gpios = <&gpio3 RK_PC1 GPIO_ACTIVE_LOW>;
		pinctrl-names = "default";
		pinctrl-0 = <&dsi1_rst_gpio>;
		reg = <0>;
		backlight = <&backlight>;
		reset-delay-ms = <50>;
		enable-delay-ms = <10>;
		prepare-delay-ms = <10>;
		unprepare-delay-ms = <10>;
		disable-delay-ms = <10>;
		init-delay-ms = <10>;
		dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST |
		 MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; 
		dsi,format = <MIPI_DSI_FMT_RGB888>;
		dsi,lanes  = <2>;
		panel-init-sequence = [
       23 01 02 7A C1    // Enable MIPI command config regsiters
       23 01 02 20 20
       23 01 02 21 E0
       23 01 02 22 13
       23 01 02 23 28
       23 01 02 24 30
       23 01 02 25 28
       23 01 02 26 00
       23 01 02 27 14
       23 01 02 28 0A
       23 01 02 29 14
       23 01 02 34 80
       23 01 02 36 24
       23 01 02 86 29
       23 01 02 B5 A0
       23 01 02 5C FF
      //  23 01 02 14 43  // Test mode 
      //  23 01 02 2A 49  // Test mode
      //  23 01 02 2A 01  // DE Polarity
       23 01 02 56 92
       23 01 02 6B 73     // PLL DIV
       23 01 02 69 18     // PLL INT
       23 01 02 10 40
       23 01 02 11 80
       23 01 02 B6 20
       23 01 02 51 20
       23 01 02 09 10
		];

		panel-exit-sequence = [
		];

		disp_timings1: display-timings {
			native-mode = <&dsi1_timing0>;
			dsi1_timing0: timing0 {
				clock-frequency = <27000000>;
				hactive = <800>;
				vactive = <480>;

				hfront-porch = <40>;
				hsync-len = <48>;
				hback-porch = <40>;

				vfront-porch = <20>;
				vsync-len = <10>;
				vback-porch = <20>;

				hsync-active = <0>;
				vsync-active = <0>;
				de-active = <0>;
				pixelclk-active = <0>;

				swap-rb = <0>;
				swap-rg = <0>;
				swap-gb = <0>;
			};
		};

		ports {
			#address-cells = <1>;
			#size-cells = <0>;

			port@0 {
				reg = <0>;
				panel_in_dsi1: endpoint {
					remote-endpoint = <&dsi1_out_panel>;
				};
			};
		};
	};

	ports {
		#address-cells = <1>;
		#size-cells = <0>;

		port@1 {
			reg = <1>;
			dsi1_out_panel: endpoint {
				remote-endpoint = <&panel_in_dsi1>;
			};
		};
	};

};